Display apparatus and method of manufacturing the same

ABSTRACT

A display apparatus includes a substrate and a plurality of pixels disposed on the substrate. Each pixel includes a gate electrode on the substrate, a common electrode insulated from the gate electrode on the substrate, a first insulating layer covering the gate electrode and the common electrode, a semiconductor pattern disposed on the first insulating layer to overlap with the gate electrode, source and drain electrodes disposed on the semiconductor pattern and spaced apart from each other, and a pixel electrode disposed on the first insulating layer to cover the drain electrode and form an electric field with the common electrode. The display apparatus may be manufactured by first to fourth photolithography processes using first to fourth masks, and the first mask may be a slit mask or a diffraction mask.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean PatentApplication No. 10-2011-0026051 filed on Mar. 23, 2011, the contents ofwhich are herein incorporated by reference in their entirety.

BACKGROUND

1. Field of Disclosure

The present invention relates to a display apparatus and a method ofmanufacturing the same. More particularly, the present invention relatesto a plane-to-line switching (PLS) mode display apparatus and a methodof manufacturing the display apparatus.

2. Description of the Related Art

A liquid crystal display includes a liquid crystal layer. Based on thedriving method of the liquid crystal layer in the display, liquidcrystal displays are classified into in-plane switching (IPS) modeliquid crystal displays, vertical alignment (VA) mode liquid crystaldisplays, and plane-to-line switching (PLS) mode liquid crystaldisplays.

The PLS mode liquid crystal display drives the liquid crystal layerusing a horizontal electric field and a vertical electric field. Theliquid crystal molecules in the liquid crystal layer of the PLS modeliquid crystal display are rotated in parallel to the plane of thesubstrate to display an image.

SUMMARY

A display apparatus with a simplified manufacturing process and reducedmanufacturing cost is provided.

A method of manufacturing the display apparatus is also provided.

A display apparatus includes a substrate and a plurality of pixelsdisposed on the substrate. Each pixel includes a gate electrode disposedon the substrate, a common electrode disposed on the substrate andinsulated from the gate electrode, a first insulating layer covering thegate electrode and the common electrode, a semiconductor patterndisposed on the first insulating layer to overlap with the gateelectrode, a source electrode disposed on the semiconductor pattern, adrain electrode disposed on the semiconductor pattern and spaced apartfrom the source electrode, and a pixel electrode disposed on the firstinsulating layer to cover the drain electrode and configured to form anelectric field with the common electrode.

The display apparatus further includes a passivation layer. In addition,the semiconductor pattern include a channel portion corresponding to anarea between the source electrode and the drain electrode and having anupper surface that is exposed, and the passivation layer covers thechannel portion.

The pixel electrode includes a trunk portion and a plurality of branchportions protruded from the trunk portion and spaced apart from eachother.

A plurality of gate lines is disposed on the substrate and extended in afirst direction and a plurality of data lines is extended in a seconddirection crossing the first direction. The first insulating layer isinterposed between the gate lines and the data lines. Each of the pixelsis connected to an adjacent gate line and an adjacent data line.

The substrate includes a display area in which the pixels are arrangedto display an image and a pad area positioned adjacent to at least oneside of the display area, and further includes a gate pad disposed inthe pad area and connected to one of the gate lines and a data paddisposed in the pad area and connected to one of the data lines.

The display apparatus may be manufactured by the following first tofourth photolithography processes.

A first photolithography process is performed using a first mask to forma first wire pattern including a gate line, a gate electrode, and acommon electrode on a substrate. An insulating layer is formed on thesubstrate to cover the first wire pattern, and a second photolithographyprocess is performed using a second mask to form a second wire patternincluding a data line and a thin film transistor electrode pattern areformed on the insulating layer. A third photolithography process isperformed using a third mask to form a third wire pattern including asource electrode, a drain electrode, and a pixel electrode on thesubstrate and form a channel portion between the source electrode andthe drain electrode. A fourth photolithography process is performedusing a fourth mask to form a passivation layer that covers the channelportion.

The first mask may be at least one of a slit mask and a diffractionmask.

In the first photolithography process, a gate pad connected to the gateline may be formed in the pad area.

In the third photolithography process, a first data pad part connectedto the data line may be formed in the pad area.

According to the above, the first substrate may be manufactured by thefirst to fourth photolithography processes using the first to fourthmasks. In addition, the number of the slit masks or diffraction masksused may be reduced, thereby reducing the manufacturing cost.

Further, the additional process of forming the spacer may be omitted,thereby simplifying the manufacturing process of the display apparatusand shortening the process time of the manufacturing method.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages will become readily apparent by referenceto the following detailed description when considered in conjunctionwith the accompanying drawings wherein:

FIG. 1 is an exploded perspective view showing a display apparatusaccording to an exemplary embodiment;

FIG. 2 is a plan view showing a portion of a first substrate of adisplay apparatus shown in FIG. 1;

FIG. 3 is a cross-sectional view taken along lines I-I′, II-II′, andIII-III of FIG. 2;

FIG. 4A is a plan view illustrating the result of a firstphotolithography process of a method of manufacturing a displayapparatus shown according to an exemplary embodiment;

FIGS. 4B to 4F are cross-sectional views illustrating the firstphotolithography process according to the lines I-I′ and II-II′ of FIG.4A;

FIG. 5A is a plan view illustrating the result of a secondphotolithography process of a method of manufacturing a displayapparatus according to an exemplary embodiment;

FIG. 5B is a cross-sectional view taken along the lines I-I′, II-II, andIII-III′ shown in FIG. 5A;

FIG. 6A is a plan view illustrating a result of a third photolithographyprocess of a method of manufacturing a display apparatus according to anexemplary embodiment;

FIG. 6B is a cross-sectional view taken along the lines I-I′, II-II, andIII-III′ shown in FIG. 6A;

FIG. 7A is a plan view illustrating the result of a fourthphotolithography process of a method of manufacturing a displayapparatus according to an exemplary embodiment;

FIG. 7B is a cross-sectional view taken along the lines I-I′, II-II, andIII-III′ shown in FIG. 6A; and

FIG. 8 is a cross-sectional view showing a display apparatus accordingto another exemplary embodiment.

DETAILED DESCRIPTION

It will be understood that when an element or layer is referred to asbeing “on”, “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layer,or intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like numbers refer to likeelements throughout. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components, regions, layersand/or sections, these elements, components, regions, layers and/orsections should not be limited by these terms. These terms are only usedto distinguish one element, component, region, layer or section fromanother region, layer or section. Thus, a first element, component,region, layer or section discussed below could be termed a secondelement, component, region, layer or section without departing from theteachings of the present disclosure.

Spatially relative terms, such as “beneath”, “below”, “lower”, “above”,“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below, depending on the orientation. The devicemay be otherwise oriented (rotated 90 degrees or at other orientations)and the spatially relative descriptors used herein interpretedaccordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting. As used herein, thesingular forms, “a”, “an” and “the” are intended to include the pluralforms as well, unless the context clearly indicates otherwise. It willbe further understood that the terms “includes” and/or “including”, whenused in this specification, specify the presence of stated features,integers, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,integers, steps, operations, elements, components, and/or groupsthereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the relevant art. It will be further understoodthat terms, such as those defined in commonly used dictionaries, shouldbe interpreted as having a meaning that is consistent with their meaningin the context of the relevant art and will not be interpreted in anidealized or overly formal sense unless expressly so defined herein.

Hereinafter, embodiments will be explained with reference to theaccompanying drawings.

FIG. 1 is an exploded perspective view showing a display apparatusaccording to an exemplary embodiment, FIG. 2 is a plan view showing aportion of a first substrate of a display apparatus shown in FIG. 1, andFIG. 3 is a cross-sectional view taken along lines I-I′, II-II′, andIII-III of FIG. 2.

According to the present exemplary embodiments, the display apparatusincludes a plurality of pixels to display an image. The displayapparatus may includes various display panels, such as a liquid crystaldisplay, an organic light emitting display panel, an electrophoreticdisplay panel, an electro-wetting display panel, amicroelectromechanical system display panel, etc. In the presentexemplary embodiment, the liquid crystal display panel will be describedas a representative example. Each of the pixels in the display apparatushave the same structure and function, and thus a single pixel and itsadjacent gate lines, data lines, and corresponding gate and data padswill be described.

Referring to FIGS. 1 to 3, the display apparatus includes a firstsubstrate SUB1, a second substrate SUB2, and a liquid crystal layer LCdisposed between the first substrate SUB1 and the second substrate SUB2.

The first substrate SUB1 includes a first insulating substrate INS1, aplurality of gate lines GL disposed on the first insulating substrateINS1, and a plurality of data lines DL disposed on the first insulatingsubstrate INS1.

The first insulating substrate INS1 includes a pixel area DA in whichthe pixels PXL are arranged and a pad area PDA positioned adjacent to atleast one side of the display area DA.

The gate lines GL and the data lines DL are arranged across the displayarea DA. The gate lines GL extend in a first direction on the firstinsulating substrate INS1. A first insulating layer ISL1 (FIG. 3) isdisposed on the first insulating substrate INS1 on which the gate linesGL are disposed. The first insulating layer ISL1 may include a firstinsulating material such as, for example, silicon nitride, siliconoxide, etc.

The data lines DL are disposed on the first insulating layer ISL1 andextend in a second direction that crosses the first direction.

Each pixel PXL is connected to one gate line GL of the two gate lines GLadjacent to the pixel PXL, and one data line DL of the two data lines DLadjacent to the pixel PXL. Each pixel PXL includes a thin filmtransistor, a common electrode CE, and a pixel electrode PE connected tothe thin film transistor.

The thin film transistor includes a gate electrode GE, a semiconductorlayer SM, a source electrode SE, a drain electrode DE.

The gate electrode GE is branched off from the gate line GL. The gateelectrode GE includes a first gate electrode GE1 disposed on the firstinsulating substrate INS1 and including a first conductive material, anda second gate electrode GE2 disposed on the first gate electrode GE1 andincluding a second conductive material. The first conductive materialmay include, for example, a transparent conductive material, such asindium tin oxide (ITO), an indium zinc oxide (IZO), indium tin zincoxide (ITZO), etc. The second conductive material may include a metalmaterial, such as, for example, copper (Cu), molybdenum (Mo), aluminum(Al), tungsten (W), chromium (Cr), titanium (Ti), or an alloy thereof.

The semiconductor layer SM is disposed on the gate electrode GE suchthat the first insulating layer ISL1 is interposed between thesemiconductor layer SM and the gate electrode GE. The first insulatinglayer ISL1 is disposed on an entire surface of the first insulatinglayer INS1 that is over the gate electrode GE to cover the gateelectrode GE.

The semiconductor layer SM includes an active layer ACT disposed on thefirst insulating layer ISL1 and an ohmic contact layer OHM disposed onthe active layer ACT. When viewed in a plan view, the active layer ACTis disposed in an area that is covered by to the source electrode SE andthe drain electrode DE and also in an area that is between the sourceelectrode SE and the drain electrode DE. The ohmic contact layer OHM isdisposed between the active layer ACT and the source electrode SE andbetween the active layer ACT and the drain electrode DE, and is notdisposed in an area between the source electrode SE and the drainelectrode DE.

The source electrode SE is branched off from the data line DL andpartially overlaps the gate electrode GE. The drain electrode DE isspaced apart from the source electrode SE and partially overlaps thegate electrode GE. The source electrode SE and the drain electrode DEmay include a third conductive material. The third conductive materialmay be a metal material, such as, for example, copper (Cu), molybdenum(Mo), aluminum (Al), tungsten (W), chromium (Cr), titanium (Ti), or analloy thereof. That is, the third conductive material may be the same asthe second conductive material.

In the present exemplary embodiment, the source electrode SE and thedrain electrode DE are overlapped with the semiconductor layer SM exceptfor the area between the source electrode SE and the drain electrode DE.The area between the source electrode SE and the drain electrode DE isused as a channel portion CH, and a portion of an upper surface of theactive layer ACT is exposed in the area between the source electrode SEand the drain electrode DE. When the thin film transistor is turned on,current flows through the channel portion CH between the sourceelectrode SE and the drain electrode DE.

A passivation layer PSV is disposed above the source electrode SE andthe drain electrode DE to cover the channel portion CH. The passivationlayer PSV includes a second insulating material such as, for example,silicon nitride or silicon oxide. The passivation layer PSV may alsocover a portion of the source electrode SE and a portion of the drainelectrode DE.

The common electrode CE is disposed on the first insulating substrateINS1 and applied with a common voltage. The common electrode CE mayinclude the same material as that of the first conductive layer. Thatis, the common electrode CE may be formed of the first conductivematerial, and the first conductive material may be a transparentmaterial, for example, indium tin oxide, indium zinc oxide, indium tinzinc oxide, etc.

The pixel electrode PE is disposed on the drain electrode DE and thefirst insulating layer ISL1. The pixel electrode PE is electricallyconnected to the drain electrode DE. The pixel electrode PE directlycontacts the upper surface of the drain electrode DE to cover the entireupper surface of the drain electrode DE.

The pixel electrode PE may include a fourth conductive material. Thefourth pixel electrode PE may include a transparent conductive material,for example, indium tin oxide, indium zinc oxide, indium tin zinc oxide,etc. In other words, the fourth conductive material may be the same asthe first conductive material.

When viewed in a plan view, the pixel electrode PE includes at least onemain portion PE1 (hereinafter, referred to as trunk portion) and aplurality of sub-portions PE2 (hereinafter, referred to as branchportions). The branch portions PE2 are arranged to be spaced apart fromeach other at regular intervals. The branch portions PE2 extend in apredetermined direction to be parallel to each other. In the presentexemplary embodiment, the trunk portion PE1 has a closed-rectangularshape and the branch portions PE2 are arranged to extend from one sideof the trunk portion PE1 to the other side, and are parallel to thelongest side of the closed-rectangle shape of the trunk portion PE1, butthey should not be limited thereto or thereby. For instance, the branchportions PE2 may be protruded from the shortest side of the trunkportion PE1 and extended in a direction substantially parallel to adirection in which the longest side of the trunk portion PE1 extends. Inaddition, the branch portions PE2 may be protruded from the trunkportion PE1 in both directions substantially perpendicular to adirection in which the longest side of the trunk portion PE1 extends.Further, the trunk portion PE1 and the branch portions PE2 may be bentseveral times, and may extend at various angles.

Gate pads GP are arranged in the pad area PDA to respectively correspondto ends of the gate lines GL, and data pads DP are arranged in the padarea PDA to respectively correspond to ends of the data lines DL. Thegate pads GP and the data pad DP are used to connect the gate lines GLand the data lines DL to external wires, thereby allowing signals to beapplied to the pixels PXL.

The gate pads GP correspond to the gate lines GL in a one-to-onecorrespondence, so that each gate line GL has a gate pad GP at the endof the gate line GL. Each gate pad GP includes a first gate pad part GP1disposed on the first insulating substrate INS1 and a second gate padpart GP2 disposed on the first gate pad part GP1. The second gate padpart GP2 includes a first opening OPN1 to expose a portion of uppersurface of the first gate pad part GP1. The first opening OPN1 is formedto prevent contact defects from occurring when external wires areconnected to the gate pads GP. The gate pad GP may be electricallyconnected to the external wires with conductive balls interposed betweenthe gate pad GP and the external wires, and thus the gate pad GP mayeasily make contact with external wires via the first opening OPN1. Inanother exemplary embodiment, conductive balls may not be applied to thegate pad GP, so that the first opening OPN1 does not need to be formedin the second gate pad GP2.

The first gate pad part GP1 may include the first conductive materialand the second gate pad part GP2 may include the second conductivematerial. In this case, the gate pad GP and the gate electrode GE may beformed through the same process, for instance in a single process.

The data pads DP are connected to the data lines DL in a one-to-onecorrespondence, so that each data line DL has a data pad DP at the endof the data line DL. Each data pad DP includes a first data pad part DP1and a second data pad part DP2 disposed on the first data pad part DP1.The second data pad part DP2 includes a second opening OPN2 to expose aportion of upper surface of the first data pad part DP1. The secondopening OPN2 is formed to prevent contact defects from occurring whenexternal wires are connected to the data pads DP. The data pad DP may beelectrically connected to the external wires with conductive ballsinterposed between the data pad DP and the external wires, and thus thedata pad DP may easily make contact with external wires via the secondopening OPN2. In another exemplary embodiment, the conductive balls maynot be applied to the data pad DP, so that the second opening OPN2 doesnot need to be formed in the second data pad DP2.

The first data pad part DP1 may be formed of the fourth conductivematerial, and the second data pad part DP2 may be formed of the secondconductive material. In this case, the first data pad part DP1 may beformed through the same process used for forming the source electrode SEor the drain electrode DE, and the second data pad part DP2 may beformed together with the passivation layer PSV through the same process.

The second substrate SUB2 includes a second insulating substrate INS2,color filters CF disposed on the second insulating substrate INS2 todisplay, for instance, red, green, and blue colors, and a black matrixBM disposed between the color filters CF to block certain light passingthrough the liquid crystal layer LC.

The first substrate SUB1 and/or the second substrate SUB2 includes aspacer (not shown) formed thereon to maintain a distance (i.e., a cellgap) between the first substrate SUB1 and the second substrate SUB2. Theliquid crystal layer LC is disposed between the first substrate SUB1 andthe second substrate SUB2.

In the above-described display apparatus, the thin film transistor isturned on in response to a driving signal provided through the gate lineGL. When the thin film transistor is turned on, an image signal providedthrough the data line DL is applied to the pixel electrode PE throughthe thin film transistor. Thus, an electric field is formed between thepixel electrode PE and the common electrode CE, and the liquid crystalmolecules in the liquid crystal layer are oriented according to theelectric field, thereby displaying the image.

Hereinafter, a method of manufacturing the display apparatus will bedescribed. First, a method of manufacturing the first substrate SUB1will be described in detail.

According to the present exemplary embodiment, the first substrate SUB1of the display apparatus may be manufactured through first to fourthphotolithography processes using four masks.

FIG. 4A is a plan view illustrating a result of a first photolithographyprocess of a method of manufacturing a display apparatus shown accordingto an exemplary embodiment, and FIGS. 4B to 4F are cross-sectional viewsillustrating the first photolithography process according to the linesI-I′ and II-II′ of FIG. 4A.

FIG. 5A is a plan view illustrating a result of a secondphotolithography process of a method of manufacturing a displayapparatus according to an exemplary embodiment, and FIG. 5B is across-sectional view taken along the lines I-I′, II-II, and III-III′shown in FIG. 5A.

FIG. 6A is a plan view illustrating a result of a third photolithographyprocess of a method of manufacturing a display apparatus according to anexemplary embodiment, and FIG. 6B is a cross-sectional view taken alongthe lines I-I′, II-II, and III-III′ shown in FIG. 6A.

FIG. 7A is a plan view illustrating a result of a fourthphotolithography process of a method of manufacturing a displayapparatus according to an exemplary embodiment, and FIG. 7B is across-sectional view taken along the lines I-I′, II-II, and III-III′shown in FIG. 6A.

In FIGS. 4B to 4F, 5B, 6B, and 7B, the display area DA including thethin film transistor, the area in which the gate pad GP is formed, andthe area in which the data pad DP is formed are sequentially presented.

Referring to FIGS. 4A to 4F, a first wire pattern is formed using afirst photolithography process. The first wire pattern includes the gateline GL, the gate electrode GE, the common electrode CE, and the gatepad GP.

In general, to form the first wire pattern, a first conductive layerCDL1, a second conductive layer CDL2, and a photoresist layer PR aresequentially stacked. Then, when the photoresist layer PR is exposed anddeveloped to form photoresist layer patterns PR1, PR2, and PR3 (FIGS. 4Cand 4D), the first and second conductive layers CDL1 and CDL2 arepatterned using the photoresist layer patterns PR1, PR2, and PR3 asmasks, thereby forming the first wire pattern.

The first photolithography process is performed as follows.

As shown in FIG. 4B, the first conductive layer CDL1, the secondconductive layer CDL2, and the photoresist layer PR are sequentiallystacked on the first insulating substrate INS1. The first conductivelayer CDL1 may be formed of the first conductive material, and thesecond conductive layer CDL2 may be formed of the second conductivematerial. The first conductive material may include the transparentconductive material, such as, for example, indium tin oxide, indium zincoxide, indium tin zinc oxide, etc. The second conductive material mayinclude the metal material, for example, copper, molybdenum, aluminum,tungsten, chromium, titanium, or an alloy thereof.

Then, the photoresist layer PR is exposed and developed using a firstmask MSK. The first mask MSK is a slit mask or a diffraction mask, andincludes a first region R1 that blocks the light, a second region R2 inwhich a slit pattern or a diffraction pattern is formed to transmit aportion of the light and block a remaining portion of the light, and athird region R3 that transmits the light.

Thus, the upper surface of the first substrate SUB1 is disposed underone of the first, second, or third regions R1, R2, and R3 of the firstmask MSK, and thus the upper surface of the first substrate SUB1 isdivided into three regions corresponding to the first, second, and thirdregions R1, R2, and R3, respectively. Therefore, the three regions ofthe first substrate SUB1 will be referred to as the first, second, andthird regions R1, R2, and R3.

When the photoresist layer PR is developed, a first photoresist patternPR1 and a second photoresist pattern PR2, which each have apredetermined thickness, remain in the first region R1 and the secondregion R2, respectively, and the photoresist layer PR is completelyremoved from the third region R3. Accordingly, the surface of the secondconductive layer CDL2 is exposed in the third region R3. In addition,because the amount of the light passing through the second region R2 ofthe first mask MSK is larger than the amount of the light passingthrough the first region R1 of the first mask MSK, the secondphotoresist pattern PR2 has a thickness that is thinner than thethickness of the first photoresist pattern PR1.

In the present exemplary embodiment, a positive-type photoresist layerin which the exposed portion of the photoresist layer is removed is usedto form the photoresist layer patterns, but the photoresist layer shouldnot be limited to the positive-type. That is, a negative-typephotoresist layer in which an exposed portion of the photoresist layerremains may alternatively be used to form the photoresist layerpatterns.

Next, the first conductive layer CDL1 and the second conductive layerCDL2 are selectively removed using the first photoresist layer patternPR1 and the second photoresist layer pattern PR2 as the masks.

Accordingly, the gate line GL, the gate electrode GE, a common electrodepattern CEP, and a gate pad pattern GPP are formed in the display areaDA.

The gate electrode GE includes the first gate electrode GE1 formed ofthe first conductive material and the second gate electrode GE2 formedof the second conductive material and disposed on the first conductivematerial. The common electrode pattern CEP includes a first commonelectrode pattern CEP1 formed of the first conductive material and asecond common electrode pattern CEP2 formed of the second conductivematerial and disposed on the first common electrode pattern CDP1.

The gate pad pattern GPP is formed in the pad area PDA. The gate padpattern GPP includes a first gate pad pattern GPP1 formed of the firstconductive material and a second gate pad pattern GPP2 formed of thesecond conductive material and disposed on the first gate pad patternGPP1.

Next, when a portion of the first photoresist layer pattern PR1 and thesecond photoresist layer pattern PR2 are removed by, for example, anashing process or an etch back process, the second photoresist layerpattern PR2 on the common electrode pattern CEP is completely removed,so that the second common electrode pattern CEP2 is exposed. Inaddition, the second photoresist layer pattern PR2 in a predeterminedregion on the gate pad pattern GPP is completely removed, and thus thesecond gate pad pattern GPP2 is partially exposed. In this case, a topportion of the first photoresist layer pattern PR1 is removed, suchportion has a thickness of the second photoresist layer pattern PR2,thereby forming a photoresist layer pattern PR3. As a result, the thirdphotoresist layer pattern PR3 remains only in the first region R1.

Next, as shown in FIG. 4E, the second common electrode pattern CEP2 anda portion of the second gate pad pattern GPP2 are removed using thethird photoresist layer pattern PR3. Thus the common electrode CE andthe gate pad GP including the first gate pad part GP1 and the secondgate pad part GP2 are formed.

As shown in FIG. 4F, the third photoresist layer pattern PR3 is thenremoved.

As a result, the gate electrode GE, the gate line GL, and the commonelectrode CE are formed in the display area DA through the firstphotolithography process, and the gate pad GP is formed in the pad areaPDA through the first photolithography process.

Referring to FIGS. 5A and 5B, the first insulating layer ISL1 is formedon the first insulating substrate INS1 on which the first wire patternis formed, and a second wire pattern is formed on the first insulatinglayer ISL1 using the second photolithography process. The second wirepattern includes the data line DL, a thin film transistor electrodepattern TEP, and a data pad pattern DPP.

To form the second wire pattern, a first semiconductor material, asecond semiconductor material, and a third conductive material aresequentially formed on the first insulating substrate INS1, a firstsemiconductor layer (not shown) including the first semiconductormaterial, a second semiconductor layer (not shown) including the secondsemiconductor material, and a third conductive layer (not shown)including the third conductive material are selectively etched using asecond mask (not shown).

The first semiconductor material may include, for example, amorphoussilicon or polycrystalline silicon. The second semiconductor materialmay include, for example, amorphous silicon doped with a dopant orpolycrystalline silicon. The second semiconductor material may be formedby injecting a dopant into the amorphous silicon or the polycrystallinesilicon. The conductive material may be a metal material including, forexample, copper, molybdenum, aluminum, tungsten, chromium, titanium, oran alloy thereof. In addition, the third conductive material may be thesame material as the second conductive material.

Accordingly, the thin film transistor electrode pattern TEP is formed inthe display area DA and includes the active layer ACT formed of thefirst semiconductor material on the first insulating layer ISL1, anohmic contact pattern OHMP formed of the second semiconductor materialon the active layer ACT, and a source/drain electrode pattern EP formedof the third conductive material on the ohmic contact pattern OHMP. Theactive layer ACT, the ohmic contact pattern OHMP, and the source/drainelectrode pattern EP are formed through a single process using thesecond mask, and thus the active layer ACT, the ohmic contact patternOHMP, and the source/drain electrode pattern EP have the same shape andare stacked on the same position when viewed in a plan view.

The data pad pattern DPP, which is formed by patterning the firstsemiconductor material, the second semiconductor material, and theconductive material, is formed in the pad area PDA.

Referring to FIGS. 6A and 6B, a fourth conductive layer (not shown) isformed using a fourth conductive material on the first insulatingsubstrate INS1 on which the second wire pattern is formed, and a thirdwire pattern is formed using a third photolithography process. Thefourth conductive material may include, for example, indium thin oxide,indium zinc oxide, or indium tin zinc oxide.

When the fourth conductive layer, which is formed of the fourthconductive material, and a portion of the thin film transistor electrodepattern TEP are selectively pattern using a third mask, the third wirepattern is formed. In detail, the fourth conductive layer and a portionof the source/drain electrode pattern EP and a portion of the ohmiccontact pattern OHMP are etched using the third mask.

As a result, the source electrode SE and the drain electrode DE areformed in the display area DA by the etching of a portion of thesource/drain electrode pattern EP, and the pixel electrode PE, whichincludes the fourth conductive material on the drain electrode DE, isalso formed. During the above-mentioned process, the ohmic contactpattern OHMP between the source electrode SE and the drain electrode DEis removed, and a portion of the upper portion of the active layer ACTis exposed while being etched. The exposed portion of the active layerACT that is between the source electrode SE and the drain electrode DEserves as the channel portion CH.

Referring to FIGS. 7A and 7B, a second insulating layer (not shown) isformed using a second insulating material on the first insulatingsubstrate INS1 on which the channel portion CH is formed. The secondinsulating material may include, for example, silicon nitride or siliconoxide. Then, a portion of the first insulating layer ISL1 and a portionof the second insulating layer are etched through a fourthphotolithography process using a fourth mask, so that the passivationlayer PSV and the second data pad part DP2 are formed. In addition, thefirst insulating layer ISL1 is removed from the area in which the gatepad GP is formed, thereby exposing a portion of the upper portion of thefirst gate pad part GP1 and the upper surface of the second gate padpart GP2 in the pad area PDA.

The passivation layer PSV covers the channel portion CH to protect thechannel portion CH. The second data pad part DP2 is etched to have thesecond opening OPN2 through which a portion of the first data pad partDP1 is exposed.

To manufacture the display apparatus, the first substrate SUB1manufactured by the above-described method is positioned opposite to thesecond substrate SUB2 on which the color filters CF are formed, and theliquid crystal layer LC is disposed between the first substrate SUB1 andthe second substrate SUB2.

As described above, in the plane-to-line switching mode displayapparatus, the first substrate SUB1 may be manufactured by using thefirst to fourth photolithography processes using, respectively, thefirst to fourth masks. In addition, the gate line GL, the gate electrodeGE, the common electrode pattern and the gate pad pattern aresimultaneously formed on the first insulating substrate INS1 through thefirst photolithography process. Therefore, among the first to fourthphotolithography processes, the slit mask or the diffraction mask isused only in the first photolithography process. Accordingly, only oneslit or diffraction mask is used to form the first substrate, and noadditional photolithography processes other than the first to fourthprocesses are used, or additional masks other than the first to fourthmasks are used, to form the first substrate. Therefore, the number ofthe slit masks or diffraction masks may be reduced in this manufacturingmethod as compared to the conventional manufacturing method of a PLSmode display apparatus, which uses two or more slit masks or diffractionmasks, and the number of to photolithography processes may also bereduced. As a result, the manufacturing costs are reduced. Further,because no additional ashing or cleaning process is required tomanufacture the display apparatus, the manufacturing process is greatlysimplified.

FIG. 8 is a cross-sectional view showing a display apparatus accordingto another exemplary embodiment. FIG. 8 shows only the first substrateof the display apparatus. In FIG. 8, the same reference numerals denotethe same elements as in FIGS. 1 to 3, and thus duplicative descriptionof the same elements will be omitted.

Referring to FIG. 8, the passivation layer PSV may be formed to have athickness corresponding to a cell gap between the first substrate SUB1and the second substrate SUB2. Thus, the passivation layer PSV may coverthe channel portion CH to protect the channel portion CH and also serveas the spacer between the first substrate SUB1 and the second substrateSUB2.

The passivation layer PSV may be formed together with the second datapad part DP2 using the fourth photolithography process. The method offorming the passivation layer PSV with the second data pad part DP2 isas follows. The second insulating layer (not shown) and the photoresistlayer are sequentially formed on the first insulating substrate INS1 onwhich the channel portion CH is formed. Then, the photoresist layer isexposed and developed using the slit mask or the diffraction mask. Thus,photoresist patterns having different thicknesses are formed indifferent regions. As shown in FIG. 4B, when the photoresist layer PR isdeveloped, a first photoresist pattern PR1 and a second photoresistpattern PR2, which each have a predetermined thickness, remain in thefirst region R1 and the second region R2, respectively, and thephotoresist layer PR is completely removed from the third region R3.Accordingly, the surface of the second conductive layer CDL2 is exposedin the third region R3. In addition, because the amount of the lightpassing through the second region R2 of the first mask MSK is largerthan the amount of the light passing through the first region R1 of thefirst mask MSK, the second photoresist pattern PR2 has a thickness thatis thinner than the thickness of the first photoresist pattern PR1.

The first insulating layer ISL1 and the second insulating layer formedunder the photoresist patterns are selectively etched using thephotoresist patterns as a mask.

Accordingly, the passivation layer PSV is formed above the gateelectrode GE to cover the channel portion CH, and the second data padpattern is formed on the first data pad part DP1. The first insulatinglayer ISL1 in the area in which the gate pad GP is formed is removedfrom the pad area PDA, and thus the portion of the upper surface of thefirst gate pad part GP1 and the upper surface of the second gate padpart GP2 are exposed.

Then, an ashing or etch back process is used to remove the portion ofthe photoresist pattern. The portion of the second data pad pattern isselectively removed using the remaining photoresist pattern as the mask,to thereby form the second data pad part DP2.

As described above, the spacer may be formed using the fourthphotolithography process during manufacture of the first substrate.Accordingly, the additional process of forming the spacer may be omittedin the present exemplary embodiments, thereby simplifying themanufacturing process of the display apparatus, shortening the processtime of the manufacturing method, and reducing the manufacturing cost ofthe display apparatus.

Although the exemplary embodiments have been described, it is understoodthat the present invention should not be limited to these exemplaryembodiments but various changes and modifications can be made by oneordinary skilled in the art within the spirit and scope of thedisclosure.

For instance, the display apparatus should not be limited to the PLSmode display apparatus. That is, the manufacturing method may be appliedto an in-plane switching mode display apparatus.

1. A display apparatus comprising: a substrate; and a plurality ofpixels disposes on the substrate, wherein each pixel comprises: a gateelectrode disposed on the substrate; a common electrode disposed on thesubstrate and insulated from the gate electrode; a first insulatinglayer covering the gate electrode and the common electrode; asemiconductor pattern disposed on the first insulating layer to overlapwith the gate electrode; a source electrode disposed on thesemiconductor pattern; a drain electrode disposed on the semiconductorpattern and spaced apart from the source electrode; and a pixelelectrode disposed on the first insulating layer to cover the drainelectrode and configured to form an electric field with the commonelectrode.
 2. The display apparatus of claim 1, further comprising apassivation layer, wherein the semiconductor pattern comprises a channelportion corresponding to an area between the source electrode and thedrain electrode and having an upper surface that is exposed, and thepassivation layer covers the channel portion.
 3. The display apparatusof claim 2, wherein the gate electrode comprises: a first conductivelayer comprising a first conductive material and disposed on thesubstrate; and a second conductive layer comprising a second conductivematerial and disposed on the first conductive layer.
 4. The displayapparatus of claim 3, wherein the common electrode comprises the firstconductive material.
 5. The display apparatus of claim 4, wherein thefirst conductive material comprises at least one of indium tin oxide,indium zinc oxide, and an indium tin zinc oxide.
 6. The displayapparatus of claim 2, further comprising: a plurality of gate linesdisposed on the substrate and extended in a first direction; and aplurality of data lines extended in a second direction crossing thefirst direction, wherein the first insulating layer is interposedbetween the gate lines and the data lines, wherein each of the pixels isconnected to an adjacent gate line and an adjacent data line.
 7. Thedisplay apparatus of claim 6, wherein the substrate comprises a displayarea in which the pixels are arranged to display an image and a pad areapositioned adjacent to at least one side of the display area, andfurther comprises a gate pad disposed in the pad area and connected toone of the gate lines and a data pad disposed in the pad area andconnected to one of the data lines.
 8. The display apparatus of claim 7,wherein the gate pad further comprises: a first gate pad part comprisinga first conductive material and disposed on the substrate; and a secondgate pad part comprising a second conductive material and disposed onthe first gate pad part, the second gate pad part being provided with afirst opening to expose a portion of the first gate pad part.
 9. Thedisplay apparatus of claim 8, wherein the data pad further comprises: afirst data pad part disposed on the substrate; and a second data padpart disposed on the first data pad and provided with a second openingto expose a portion of the first data pad part.
 10. The displayapparatus of claim 9, wherein the first data pad part comprises a samematerial as the pixel electrode and the second data pad part comprises asame material as the passivation layer.
 11. The display apparatus ofclaim 1, wherein the pixel electrode comprises a trunk portion and aplurality of branch portions protruded from the trunk portion and spacedapart from each other.
 12. A method of manufacturing a displayapparatus, comprising: performing a first photolithography process usinga first mask to form a first wire pattern including a gate line, a gateelectrode, and a common electrode on a substrate; forming an insulatinglayer on the substrate to cover the first wire pattern; performing asecond photolithography process using a second mask to form a secondwire pattern including a data line and a thin film transistor electrodepattern on the insulating layer; performing a third photolithographyprocess using a third mask to form a third wire pattern including asource electrode, a drain electrode, and a pixel electrode on thesubstrate and form a channel portion between the source electrode andthe drain electrode; and performing a fourth photolithography processusing a fourth mask to form a passivation layer that covers the channelportion.
 13. The method of claim 12, wherein the first mask is at leastone of a slit mask and a diffraction mask.
 14. The method of claim 13,wherein the first photolithography process comprises: sequentiallydepositing a first conductive material and a second conductive materialon the substrate to form a first conductive layer and a secondconductive layer; and etching a portion of the first conductive layerand a portion of the second conductive layer using the first mask. 15.The method of claim 14, wherein the etching of the first and secondconductive layers comprises: forming a photoresist layer on the secondconductive layer; exposing and developing the photoresist layer usingthe at least one of the slit mask and the diffraction mask to form afirst photoresist layer pattern having a first thickness in a firstregion and a second photoresist layer having a second thickness smallerthan the first thickness in a second region different from the firstregion; etching a portion of the first photoresist layer pattern and aportion of the second photoresist layer pattern using the first andsecond photoresist layer patterns as a mask; ashing the first and secondphotoresist layer patterns to form a third photoresist layer patternhaving a third thickness smaller than the first thickness in the firstregion; and etching the second conductive layer using the thirdphotoresist layer pattern as a mask to form the gate line and the gateelectrode in the first region and the common electrode in the secondregion.
 16. The method of claim 12, wherein the second photolithographyprocess comprises: sequentially forming a first semiconductor layerincluding amorphous silicon or polycrystalline silicon, a secondsemiconductor layer including amorphous silicon doped with a dopant orpolycrystalline silicon doped with the dopant, and a third semiconductorlayer including a third conductive material on the insulating layer; andetching the first semiconductor layer, the second semiconductor layer,and the third conductive layer using the second mask to form an activelayer, an ohmic contact pattern, and a semiconductor electrode pattern.17. The method of claim 16, wherein the third photolithography processis to each a portion of the ohmic contact pattern and a portion of thesemiconductor electrode pattern using the third mask to form the sourceelectrode, the drain electrode spaced apart from the source electrode,and the channel portion.
 18. The method of claim 12, wherein thesubstrate comprises a display area in which the pixels are arranged todisplay an image and a pad area positioned adjacent to at least one sideof the display area, and the first photolithography process furthercomprises forming a gate pad disposed in the pad area and connected tothe gate line.
 19. The method of claim 18, wherein the forming of thegate pad comprises: forming a first gate pad part on the substrate; andforming a second gate pad part on the first gate pad part, the secondgate pad part including a first opening to expose a portion of an uppersurface of the first gate pad part.
 20. The method of claim 19, whereinthe first gate pad part is formed of the first conductive material andthe second gate pad part is formed of the second conductive material.21. The method of claim 18, wherein the third photolithography processfurther comprises forming a first data pad part disposed in the pad areaand connected to the data line, and the fourth photolithography processfurther comprises forming a second data pad part disposed on the firstdata pad part and including a second opening to expose a portion of anupper surface of the first data pad part.
 22. The method of claim 21,wherein the second data pad part is formed of a same material as thepassivation layer.